CAN Bit Timing Step by Step

A CAN controller does not take a baud rate. It takes a prescaler and a handful of segment lengths, and several different combinations give the same bit rate with different behaviour on a real bus. This guide works through the choice by hand for a 36 MHz clock at 500 kbit/s, then shows what changes with other clocks. The register examples use the STM32 bxCAN CAN_BTR layout.

The parts of one bit

The controller divides its clock by the prescaler (BRP) to get a time quantum, written tq. One bit is a whole number of quanta, split into four segments:

The bus is sampled at the boundary between Phase_Seg1 and Phase_Seg2. bxCAN does not separate Prop_Seg from Phase_Seg1. It has one field, TS1, for both, and TS2 for Phase_Seg2. So:

quanta per bit = 1 + TS1 + TS2
bit rate       = clock / (BRP × quanta per bit)
sample point   = (1 + TS1) / quanta per bit

The field limits are BRP 1 to 1024, TS1 1 to 16, TS2 1 to 8 and SJW 1 to 4.

Step 1: find the quanta counts your clock allows

Divide the clock by the bit rate. For 36 MHz and 500 kbit/s that is 72. BRP and the quanta count are both integers and their product must be exactly 72, so only the divisors of 72 are available. Within the usual range of 8 to 25 quanta per bit:

This table is the whole design space. Any setting not in it gives a bit rate that is not 500 kbit/s. A setting that is slightly off, say 16 quanta with BRP 4 for 562.5 kbit/s, will not work at all: resynchronisation corrects small oscillator differences between nodes, not a 12% error in the bit rate.

Step 2: choose the sample point

The sample point is a trade between two needs. A late sample point leaves more of the bit for the signal to propagate and settle, which matters on long buses. An early one leaves a longer Phase_Seg2, which gives more room to resynchronise against other nodes' oscillators. For classical CAN, CiA recommends 87.5% for bit rates up to 800 kbit/s and 75% at 1 Mbit/s, and following the recommendation is the simplest way to match the other nodes on the bus.

With 36 MHz, exactly 87.5% is only reachable with 8 quanta. The 18-quanta option gets 88.9%, which is close enough to interoperate. The step column shows why more quanta are useful in general: with 8 quanta the only choices near the target are 75% and 87.5%, while 18 quanta gives 83.3% and 88.9% as well.

Step 3: check the propagation delay

During arbitration and the acknowledge slot, a node must see another node's bit within the same bit time. In the worst case a signal travels from one end of the bus to the other and the reply travels back. Prop_Seg must cover that round trip, including the delay through the transceivers and controllers at both ends.

As a worked example, assume 5 ns per metre of cable and 150 ns of transceiver and controller delay per node. Take the real figures from your cable and transceiver datasheets.

With 8 quanta and TS1 = 6, a 40 m bus needs 3 tq of propagation time, which leaves 3 tq for Phase_Seg1. At 100 m the propagation time takes all 6 tq of TS1 and nothing is left for Phase_Seg1. That bus is at the limit for 500 kbit/s under these assumptions, which is why long buses run at lower bit rates.

Step 4: set SJW

Nodes resynchronise on every recessive-to-dominant edge. If the edge arrives late, the controller lengthens Phase_Seg1; if it arrives early, it shortens Phase_Seg2. SJW is the maximum correction per edge, in quanta. A larger SJW tolerates more difference between the nodes' oscillators.

SJW must not exceed either phase segment. With TS2 = 1, SJW can only be 1. This is the price of the 8-quanta setting: the 87.5% sample point leaves a single quantum after the sample. With 18 quanta, TS2 = 2 allows SJW = 2. When the nodes use crystals, SJW = 1 is normally enough. When a node runs from a ceramic resonator or an internal oscillator, prefer a setting whose Phase_Seg2 allows a larger SJW.

Step 5: build the register value

In CAN_BTR, BRP occupies bits 9:0, TS1 bits 19:16, TS2 bits 22:20 and SJW bits 25:24. Every field stores the value minus one.

Forgetting the minus one is the most common mistake here. Writing 6 into the TS1 field gives 7 quanta, a bit of 9 quanta instead of 8, and a bit rate of 444 kbit/s.

When the clock does not cooperate

Clocks of 8, 16 and 48 MHz divide cleanly: all of them reach 500 kbit/s with 8 or 16 quanta, and both of those hit 87.5% exactly. Other clocks do not. A 42 MHz peripheral clock, common on 168 MHz STM32F4 designs, gives a ratio of 84 at 500 kbit/s. Its divisors in range are 12, 14 and 21:

No combination gives 87.5%. The 14-quanta setting at 85.7% (CAN_BTR = 0x001A0005) is the usual choice and works with nodes at 87.5%. If an exact match matters, the fix is in the clock tree, not in the CAN registers: pick a PLL configuration whose peripheral clock is a multiple of 8 MHz.

Checks before blaming the software

• Every node uses the same bit rate, and sample points within a few percent of each other.
• The peripheral clock in your calculation is the one the CAN peripheral really gets. A wrong assumption about the bus prescaler is a frequent cause of a bit rate that is off by a factor of two.
• The bus is terminated with 120 Ω at each end. With power off, the resistance between CAN_H and CAN_L should read about 60 Ω.
• A node alone on the bus never gets an acknowledge and will report errors. Test with at least two nodes, or use loopback mode.
• Measure one bit on an oscilloscope: 2 µs at 500 kbit/s, 4 µs at 250 kbit/s, 8 µs at 125 kbit/s.

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