UART Baud Rate Calculator
Calculate actual baud rate and error percentage from MCU system clock.
| Baud Rate | Actual | Error | Status |
|---|
UART (Universal Asynchronous Receiver-Transmitter) requires both devices to agree on a baud rate within tight timing tolerances.
Formulas:
- Exact Baud Rate:
Baud = Clock / (Oversampling * USART_DIV) - Error %:
((Actual - Target) / Target) * 100 - Frame Time:
(Data + Parity + Stop + Start bits) / Baud
Usage: Input the system clock and target baud rate. An error rate of ≤ 0.5% is excellent, ≤ 2% is acceptable, and anything above 2% may cause data corruption.
When you need it: Choosing a baud rate the MCU's clock can actually generate within tolerance, or diagnosing garbled bytes that come from too much baud error between two devices.
Worked example: 16 MHz clock, 115200 baud, 16× oversampling → USARTDIV = 16e6 / (16 × 115200) = 8.68. Rounding to 9 gives an actual 16e6 / (16 × 9) = 111111 baud, an error of (111111 − 115200) / 115200 = −3.5% — over budget. A fractional baud generator or 8× oversampling closes the gap.
Tips & gotchas:
- Keep total baud error under about ±2%; a UART samples mid-bit and accumulates error across ~10 bits per frame, so ±2.5% is roughly the breaking point.
- Both ends must agree within their combined tolerance — a −1.5% transmitter and +1.5% receiver already eat the whole margin.
- Fractional (fixed-point) baud dividers on modern MCUs cut the error dramatically versus integer-only dividers.
- High baud rates (≥ 921600) need a clean crystal-derived clock; internal RC oscillators drift with temperature and voltage.
Baud rate error by clock and divider type
Error for the standard baud rates with 16× oversampling. An integer divider (AVR-style) can only divide the clock by whole numbers; a fractional divider (STM32-style BRR) divides in 1/16 steps.
| Baud | 8 MHz integer | 16 MHz integer | 16 MHz BRR | 16 MHz fractional | 72 MHz BRR | 72 MHz fractional |
|---|---|---|---|---|---|---|
| 9,600 | +0.16% | +0.16% | 0x0683 | -0.02% | 0x1D4C | 0% |
| 19,200 | +0.16% | +0.16% | 0x0341 | +0.04% | 0x0EA6 | 0% |
| 38,400 | +0.16% | +0.16% | 0x01A1 | -0.08% | 0x0753 | 0% |
| 57,600 | -3.55% | +2.12% | 0x0116 | -0.08% | 0x04E2 | 0% |
| 115,200 | +8.51% | -3.55% | 0x008B | -0.08% | 0x0271 | 0% |
| 230,400 | +8.51% | +8.51% | 0x0045 | +0.64% | 0x0139 | -0.16% |
| 460,800 | +8.51% | +8.51% | 0x0023 | -0.79% | 0x009C | +0.16% |
| 921,600 | -45.75% | +8.51% | 0x0011 | +2.12% | 0x004E | +0.16% |
Frequently asked questions
What baud rate error is acceptable?
Up to 0.5% is excellent and up to 2% is acceptable. Above 2% data corruption becomes likely. The errors of both ends add up, so a −1.5% transmitter talking to a +1.5% receiver has already used the whole margin.
Why does 115200 baud fail with a 16 MHz clock and an integer divider?
16,000,000 / (16 × 115200) = 8.68. Dividing by 9 gives 111,111 baud (−3.55%) and dividing by 8 gives 125,000 baud (+8.51%). Switching to 8× oversampling gives 16,000,000 / (8 × 17) = 117,647 baud, +2.12%, which is still marginal.
Which clock frequencies give 0% baud error?
Clocks that are a whole multiple of 16 × 115200 = 1.8432 MHz: 1.8432, 3.6864, 7.3728, 11.0592, 14.7456 and 18.432 MHz. They divide exactly to 115200 baud and to every standard rate below it.
How do I get the STM32 BRR value?
With 16× oversampling BRR = round(f_CK / baud). At 72 MHz and 115200 baud that is 72,000,000 / 115200 = 625 = 0x0271: mantissa 0x27 = 39, fraction 1/16, and the actual baud rate is exactly 115200.