Embedded Calculators & Part Finder
Size a value with 64 free calculators, then find the real component that fits — in stock, at the best price. For MCU, power, RF & firmware. No account.
★ Popular
💡LED Resistor
⚡Ohm's Law
🚌CAN Bit Timing
🔻Voltage Divider
🔠Glyph Mapper
📦Struct Padding
PWM / Timer
Frequency, period, duty cycle
UART Baud Rate
Error rate, PASS/FAIL check
ADC Resolution
LSB voltage, SNR, dynamic range
Watchdog Timer
STM32 IWDG & WWDG timeouts
I2C Timing
Bus timing & pull-up values
CAN Bus Bit Timing
STM32 bxCAN/FDCAN & MCP2515
SPI Timing
Bit period, frame, throughput
RS-485 Bus
Cable length, termination, bias
LIN Bus Timing
Bit, break, frame time
Modbus RTU Timing
Char & inter-frame gaps
Ring Buffer / DMA
Buffer sizing
Register Map → C
Bitfield struct & macros
CRC → C Code
Lookup table & function
Stepper Motor
Steps/rev, microstep, pulse rate
BLDC / PMSM Speed
Motor electrical freq, pole pairs
Rotary Encoder
Motor encoder counts/rev
Motor Torque ↔ Power
N·m, RPM, Watts, hp
MOSFET Power Loss
Conduction & switching loss
Transformer Turns
Ratio, Ns, current ratio
LDO Dropout / Power
Heat dissipation & efficiency
I2S Audio Clock
BCLK, LRCLK, bit period
USB Data Lines
Bit time, 90Ω, termination
Ethernet Cable
Bit time, delay, 100m limit
Bit Field Visualizer
32-bit register breakdown
Q-Format Converter
Float ↔ fixed-point
Number Base Converter
Dec, Hex, Bin, Oct converter
IEEE 754 Visualizer
32-bit Float & 64-bit Double
Endian Swap
Big/Little/Mid-Endian byte swap
Struct Alignment
C struct padding & visualizer
Memory & Transmission
Bytes, baud rate & sample times
Glyph Mapper
7-Segment & Character LCD custom font generator
Crystal Load Cap
Oscillator load capacitor sizing
Ohm's Law
V, I, R, P — any 2 → all 4
Voltage Divider
Vout, loaded divider, Thevenin
LED Resistor
Series/parallel configs & E24
Resistor Code
Color bands & SMD decoder
Op-Amp Gain
Amp configurations & Schmitt
Instrumentation Amp
3-op-amp in-amp gain & Vout
Op-Amp Resistor
Inverting/Non-inv → R2,R3,R4
BJT Bias CE
Q-point & stability factor
NE555 Timer
Astable / monostable
Capacitor Charge
RC time constant, τ milestones
Buck / Boost
Switching regulator design
AWG Wire Gauge
Wire gauge & voltage drop
Series / Parallel
R · C · L equivalent value
LM317 Regulator
Adjustable Vout & R2 solver
Current Divider
Branch currents in parallel R
LC Resonance
LCR resonant freq, Q-factor
RC Filter
Cutoff frequency, gain & phase
dB Converter
dB, dBm & mW bidirectional
CRC Calculator
CRC-8/16/32, 7 polynomials
Checksum / CRC
XOR, Sum8/16, LRC, CRC
PCB Trace Calc
IPC impedance & trace width
Active Filter
Sallen-Key 2nd-order LPF/HPF
RF Trans. Line
Microstrip impedance (IPC-2141)
VSWR / Return Loss
Γ, return & mismatch loss
RF Link Budget
FSPL, Rx power, margin
Wavelength / Antenna
λ, λ/2 dipole, λ/4 whip
Attenuator Pad
T / Pi resistor values (dB)
Coil Inductance
Air-core solenoid (Wheeler)
Battery Life
Estimated system run-time
Temperature
Units & RTD sensor temps
Wheatstone Bridge
Bridge Vout & balance
Junction Temp
Thermal Tj & max power
SPI Bus Timing Calculator
Bit period, frame time and throughput for an SPI bus.
Input
ℹ SPI moves 1 bit per SCK edge, so throughput = SCK.
Find Component lists logic level shifters for cross-voltage SPI (e.g. 3.3 V ↔ 1.8/5 V) — pick one rated above your SCK rate.
Find Component lists logic level shifters for cross-voltage SPI (e.g. 3.3 V ↔ 1.8/5 V) — pick one rated above your SCK rate.
Results
Bit Period—
Frame Time—
Throughput—
💡 Usage & Formula
bit period = 1/SCK, frame time = bits/SCK, throughput = SCK (1 bit per clock).
When you need it: Confirming an SCK frequency the slave can accept, and checking that setup/hold plus trace flight-time still leave a valid sampling window at high clock rates.
Worked example: SCK = 10 MHz → bit period 100 ns; a 24-bit frame takes 24 × 100 ns = 2.4 µs and throughput is 10 Mbit/s (one bit per clock). Push to 50 MHz over 15 cm of FR-4 (~1 ns each way) and the round-trip flight time starts eating the read window.
Tips & gotchas:
- At high SCK the slave's output-valid time plus trace delay can force a lower clock or a delayed sampling phase.
- CPOL/CPHA (SPI mode) must match on both ends, or every byte is shifted/inverted.
- Add series (source) termination on SCK for long traces to tame ringing and overshoot.
- Respect CS-to-first-clock setup and last-clock-to-CS hold; many slaves latch on the CS edge.
📖 References:SPI (Wikipedia)